Introduction
As semiconductor technology advances into the Angstrom era, chipmakers are turning to new architectural innovations to overcome the physical limits of traditional frontside power delivery. One such breakthrough is the Backside Power Delivery Network (Backside PDN), a game-changing approach that routes power lines from the back of the wafer rather than the front, dramatically improving performance, power efficiency, and scalability.
In this article, we’ll explore what Backside PDN is, how it works, key players in the industry adopting it, and what metrology solutions are required to support its implementation.
What is Backside PDN?
In conventional chip design, both data signals and power lines are routed on the front side of the silicon wafer. However, this setup has become increasingly inefficient due to congestion and rising IR drops as nodes shrink. Backside PDN resolves this by relocating power delivery routes to the backside of the wafer, enabling better signal integrity and lowering resistance and voltage drop.
Key Benefits:
- Reduced IR drop and improved power integrity
- Higher signal density on the front side
- Better thermal performance and cooling
- Scalability for advanced nodes (3nm and below)
How Does It Work?
Backside PDN uses TSVs (Through-Silicon Vias) and hybrid bonding to connect the backside metal layers with the transistors and front-side routing. Power is supplied directly from the wafer backside, bypassing congested front-side metal layers. The signal lines remain on the front side, eliminating interference.
This structure is often combined with wafer thinning, backside metallization, and complex bonding steps.
Who’s Leading the Charge?
- Intel: Their “PowerVia” technology is the first implementation of full backside power delivery at scale, expected in the Intel 20A node.
- TSMC: Backside PDN is planned in their roadmap for N2 and A16 nodes.
- Samsung: Rumored to be developing backside PDN in parallel with GAA improvements.
These innovations are being touted as essential enablers for next-generation HPC, AI, and mobile SoCs.
What Metrology Tools Are Required?
Because the power layer is now moved to the backside, advanced metrology is required for:
🔍 Key Inspection Areas:
- TSV alignment and defect detection (via IR Scope, SAM)
KIR-6120 Infrared Inspection Microscope – kovistechnology blog
- Backside metal layer uniformity (3D profiler, ellipsometry)
- Warpage control after thinning and bonding ( TTV/Warpage tools)
WARP-3500: High-Precision Wafer Thickness and Shape Measurement System – kovistechnology blog
Challenges and Considerations
- Thermal mismatch during thinning and bonding
- Mechanical stress and warpage in ultra-thin wafers
- Alignment accuracy for hybrid bonding and TSVs
- New types of defects on the backside requiring different inspection strategies
All these demand collaboration between process engineers and metrology experts.
Conclusion
Backside PDN is no longer just a research topic—it is rapidly becoming a cornerstone of cutting-edge chip design. By separating power and signal routes across the wafer’s two faces, manufacturers are unlocking new levels of density, performance, and energy efficiency.
However, to make this a production reality, advanced metrology solutions will play a critical role. Understanding these requirements now gives fabs and equipment makers a strong competitive edge.
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