Introduction
In the current era of AI and massive-scale big data workloads, GPUs and accelerators (XPUs) must process exponentially larger datasets. As a result, memory bandwidth (the speed at which data is transferred) and latency issues have emerged as a critical bottleneck known as the “Memory Wall.”
While HBM (High Bandwidth Memory) up to HBM3E has been introduced to solve these problems, simply stacking DRAM dies and connecting them is no longer enough.
Root Cause
The HBM structure vertically stacks multiple DRAM dies (3D stacking), with the Base Die positioned at the bottom. Traditionally, the base die handled memory operations, control, data routing, and interconnect paths.
However, several limitations have surfaced:
-
The interface width between memory and host processors (e.g., GPU) has reached physical limits, making further scaling extremely difficult.
-
If the base die remains a passive “connection-only” component, it cannot meet new demands for compute assistance, power optimization, energy efficiency, and interface customization.
-
To implement these new features, DRAM process technology alone is insufficient—logic process technology must be introduced into the Base Die.
Solution
This has led to the transition from a traditional passive base die to a logic-based base die.
In other words, the base die is evolving into a Logic Die that performs critical system-level functions instead of acting merely as a structural foundation for DRAM stacking.
Key Enhancements
-
Expanding interface width (e.g., 2048-bit interface in HBM4) for higher bandwidth.
-
Improving memory-to-host data flow efficiency.
-
Enhanced power and energy management inside the base die (power delivery, refresh control, etc.).
-
Custom HBM design optimized for specific accelerators.
As a result, the bottleneck between memory and host processors significantly decreases, improving overall compute efficiency. More importantly, the base die becomes a strategic differentiator, fundamentally altering the semiconductor ecosystem.
Why Is the Base Die Becoming Critical Now?
As AI models such as Generative AI and Large Language Models (LLMs) scale rapidly, demand for memory capacity and bandwidth has surged. Traditional HBM improvements—adding more DRAM layers and slightly increasing interface speeds—are reaching physical limits such as:
-
TSV (Through-Silicon-Via) complexity
-
Stack height limits
-
Fine-pitch packaging challenges
Additionally, without transitioning the base die from DRAM-specific process to logic process, achieving high-speed interfaces and customization becomes impossible.
HBM4 Requirements
-
Interface width doubled to 2048-bit
-
12-Hi and 16-Hi stacking
-
Logic foundry processes (e.g., 12nm, 4nm, even 3nm) are required for speed, power, and thermal optimization.
This transformation requires foundry collaboration, meaning memory alone cannot solve scaling challenges—companies like TSMC must deeply participate in base die design and production.
Effect
Switching the base die to a logic-based architecture enables:
-
Reduced memory-to-host bottlenecks
-
Higher compute efficiency for AI accelerators and HPC systems
-
Strong product differentiation and increased entry barriers
-
New competition across memory, foundry, and packaging ecosystems
Roadmap: HBM4 + Base Die Transition
Key Specification Changes
-
2048-bit interface bandwidth
-
DRAM stack height 4-Hi / 8-Hi / 12-Hi / 16-Hi
-
Base Die logic nodes: 12nm / 4nm / 3nm depending on vendor strategy
Market Deployment
-
SK Hynix supplied 12-Hi HBM4 samples in March 2025, targeting 16-Hi in 2026.
-
SK Hynix leverages TSMC foundry for logic base die production.
-
Samsung likely to use internal 4nm node.
-
Micron is expected to adopt 12nm or smaller nodes via TSMC.
-
For future HBM4E, 3nm logic nodes are expected to be applied.
Process Risks and Challenges
Micro-bump / Hybrid Bonding Issues
-
Head-in-pillow, solder deformation, solder necking, micro cracks
3D Architecture Complexity
-
TSV alignment and stacking yield risk increases as layer count grows
Yield and Cost Burden
-
Logic node adoption reduces yield and sharply increases cost
Thermal & Power Packaging Constraints
-
Dense stacking leads to heat concentration and reliability issues
-
Short shoreline limits package design freedom
Recommended Inspection / Metrology Tools
-
C-SAM inspection for micro-bump joint evaluation inside HBM stack
Contact & Demo Request
Atlantis is more than a measurement instrument —
it’s a key enabler for process quality, efficiency, and reliability.
We’re Here to Help
We warmly welcome any inquiries regarding product specifications or pricing.
With English-speaking staff on our team, we’re well-prepared to assist you efficiently and clearly.
Please don’t hesitate to contact me directly — I will personally respond to your email.
You can reach me at: hy.kang@kovistek.com