Hello, and welcome to our deep dive into semiconductor packaging challenges.
Today, we’re focusing on a persistent issue in flip-chip packaging: underfill voids.
Underfill is a critical process that fills the gap between the chip and substrate bumps to provide mechanical stability and improve thermal dissipation. However, many wonder:
“Why do defects and failures still occur even after underfilling?”
The culprit is often tiny voids trapped inside the underfill material.
What is Underfill?
In flip-chip packaging, micro bumps connect the chip directly to the substrate.
Underfill is the epoxy or resin injected into the gap to strengthen the connection and protect the bumps.
Simply put, underfill acts like a ‘glue’ that holds the chip firmly in place.
Why Do Voids Form Inside Underfill?
A void is an air bubble or trapped gas inside the underfill.
Even small voids can lead to cracks, delamination, or open failures under stress.
Common Causes of Underfill Voids:
| Cause | Explanation |
|---|---|
| Uneven dispensing | Underfill does not fully cover the chip gap uniformly |
| Incorrect viscosity | Too thin causes bubbles, too thick impairs flow |
| Insufficient pre-bake | Moisture and gases not fully removed, leading to trapped air |
| Improper temperature profile | Curing at incorrect temps causes shrinkage and void formation |
| Material-process mismatch | Optimal conditions not met between resin and process |
Visualizing Voids
Google image search keywords:Underfill void microscope image, Flip chip encapsulation defect
X-ray and C-SAM inspections reveal many voids not visible to the naked eye, often located in critical stress areas.
How to Prevent Voids?
Eliminating voids is crucial for reliability. Typical solutions include:
-
Optimizing dispensing speed to ensure smooth flow from chip edges inward
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Adequate pre-bake to remove moisture and outgassing
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Vacuum-assisted underfill processes to minimize trapped air
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Adjusting viscosity and curing temperature profiles
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Strengthening automated inspection with AOI or C-SAM to detect voids early
Why Does This Matter?
Just one void can cause catastrophic failure during thermal cycling or mechanical stress tests.
Underfill voids can propagate cracks that cause electrical open circuits, reducing overall device reliability and yield.
Closing Thoughts
Underfill is not just glue; it’s the last line of defense for chip reliability.
But even a tiny trapped bubble can compromise the entire package.
Stay tuned for upcoming posts on:
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How to select optimal underfill materials
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Best practices for void-free dispensing
KOVIS INSPECTION (C-SAM)
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You can reach me at: hy.kang@kovistek.com
